1. Field of the Invention
The present invention relates to a processor for signal processing provided for integration in a single module and intended to be associated with other signal processing circuits (particularly other processors) to form a hierarchical multiprocessing structure, this processor being formed from a signal processing device operating according to instructions transmitted by an instruction bus line.
2. Description of the Prior Art
In equipment used in telecommunications, for example in modems for data transmission, digital processing of the signal is carried out and the current tendency is to perform all the required functions by means of programmable processors. The digital processing of the signal is characterized by arithmetic operations (addition, subtraction, multiplication, division) executed repetitively on relatively simple data structures. The microprocessors in general use are not suitable for the digital processing of the signal mainly because of their low performance in speed of execution and the inadequacy of their architecture and of their instruction set.
Fully integrated processors are commercially available which are oriented towards signal processing and which are distinguished from general purpose microprocessors by their instruction execution time which is in the order of 250 ns, by the high degree of internal parallelism of operations and by an instruction set suited to the calculations to be made, including, in particular, multiplication.
But in order to perform all the functions required, for example in a modem, transmission, reception, equalization, or echo cancelling, it is usually necessary to associate several signal processor units in order to distribute the tasks to be carried out. Commercial signal processors have only one data access per unit for the data exchanges with the exterior and can only be associated by connecting these accesses to a common data bus such that, throughout the time during which this common bus is being used for exchanges between two processors or between a processor and a memory connected to the bus, the bus is not available for exchanges between other processors. This results in a loss of time and a complicated management of the set of processors, particularly in the case in which certain exchanges take up the majority of the time. This happens, for example, when producing the automatic echo cancelling function in a modem, which necessitates almost continuous exchanges between a RAM memory containing coefficients and the processor which has to update those coefficients.
The invention also relates to a hierarchical multiprocessing structure including at least one such processor.
A tree structure, with a limited number of processors connected to the same data bus, seems more suited to the processing to be carried out in devices of the modem type. Such a structure used for signal processing is described in U.S. Pat. No. 4,096,566. In this known structure, each processor is formed from several modules, a control module and an arithmetic module connected to an internal data bus and a bus adapter module for the connection with another processor. Each control module can perform a master function with respect to one or more control modules and can itself be a slave for a higher level control unit. In this known structure, a single internal bus connects the bus adapter of the master processor to the bus adapter of the slave processor, which does not allow independence between the data exchanged by a processor with its master processor and its slave processor. The data exchanges between master and slave processors are carried out using an interrupt procedure which produces an undesirable loss of time.